Silicon complementary metal-oxide-semiconductor (Si-CMOS) has dominated the semiconductor industry for the last five decades, leading to sustained and significant technological advancements in integrated circuits (ICs) and microelectronics, through application of Moore's Law scaling of CMOS transistor devices. However, the most advanced CMOS devices of today have shrunk to the point where they are only on the order of a few atoms in size, and are fast approaching a point where physics and economics will preclude further meaningful scaling. Thus, any future IC performance gains likely need to be achieved using different approaches, of which one of the most promising is to use new semiconductor materials to produce hybrid devices, such as compound semiconductors (e.g. III-V semiconductors and etc.), that have better electrical and optical properties than silicon. The most beneficial way to utilize the new materials is not to have them replace silicon entirely, but to adopt each material for manufacturing specific functional portions of an integrated circuit. For instance, the high integration density of Si-CMOS makes it ideal for producing functional portions intended for digital processing and logic applications, whereas various III-V materials are highly suitable for manufacturing functional portions intended for optoelectronic and RF/wireless applications, and high energy-storage density Li-based materials are optimal for producing integrated micro-batteries. The challenge therefore is to monolithically integrate the different types of materials such that the different functional portions of the circuits are able to work together seamlessly and efficiently, while occupying minimal chip footprint.
Practical monolithic integration requires different materials to be processed within CMOS circuits in commercial CMOS fabrication facilities, without compromising the standard CMOS manufacturing processes (i.e. no contamination). This is because, due to massive investment over the past decades, the CMOS industry and infrastructure are the most developed and advanced, compared with the equivalent for other types of electronic materials. As a result, this generally requires that non-CMOS materials, which are typically perceived as (and sometimes, in very specific situations, are considered real) CMOS contaminants, are never etched or exposed during processing by CMOS compatible tools.
In this regard, there is a recent report in literature on prevention of cross-contamination between CMOS and III-V materials, where the solution proposed is to selectively grow the III-V layers (of an LED) and then cap the III-V materials with a thin layer of silicon—see FIG. 1. The bottom contact of the LED is accessed through the 100% germanium (Ge) cap of a silicon-on-lattice-engineered substrate (SOLES) wafer 100, as shown in FIG. 1.
However, in cases where completed non-CMOS layers are displaced above or under the Si-CMOS layer(s), the non-CMOS materials (of the layers) may still potentially be exposed at the edges of the associated wafers, since the non-CMOS regions are not confined within oxide wells, similar to the case in the SOLES wafer 100.
One object of the present invention is therefore to address at least one of the problems of the prior art and/or to provide a choice that is useful in the art.